1. Field of the Invention.
The present invention relates to devices and methods for making semiconductor devices, and in particular to a thin film device and method for fabricating a thin film device.
2. Description of the Related Art.
Present Integrated Circuit (IC) technologies allow for the creation of very high speed and high-performance circuits through the use of High Electron Mobility Transistors (HEMT) as well as Heterojunction Bipolar Transistor (HBT) technology. However, the HEMT and HBT IC technologies cannot readily use fabrication techniques that are required for other desired IC components. For example, techniques to make thin film resistors are currently not compatible with HEMT and HBT fabrication techniques.
A related art discussed in “An InP-based HBT fab for high-speed digital, analog, mixed-signal, and optoelectronics ICs,” W. E. Stanchina, J. F. Jensen, R. H. Walden, M. Hafizi, H. C. Sun, T. Liu, G. Raghavan, K. E. Elliott, M. Kardos, A. E. Schmitz, Y. K. Brown, M. E. Montes, M. Yung, in 1995 GaAs IC Symposium Technical Digest, pp. 31-34, which is incorporated by reference herein, describes the methodology of fabricating HBT based ICs. To fabricate a thin film resistor on an HBT, a layer of silicon nitride (SiN) is deposited over the entire wafer to protect other devices from short circuiting. A layer of tantalum nitride (TaN), which is to be used for the thin film resistor, is then sputter deposited over the SiN. A photoresist layer is then patterned through photolithographic techniques. The TaN/SiN is then etched using a Reactive Ion Etch (RIE) technique. To assure complete removal of the underlying SiN layer, overetch of the TaN/SiN is performed, which preferentially undercuts the SiN over the TaN due to the differences in the etch rates. When metal is then evaporated for interconnects, the metal breaks at the undercut between the SiN underlayer and the TaN resistor. The SiN/TaN layers form a stack, or step, and the metallization layer cannot fill in the intersection of the SiN/TaN and surface, which is known as poor step coverage. As such, thin film resistors cannot be readily used as an integrated package with HBT devices.
HEMT devices suffer even greater degradation when combined with thin film resistors because the RIE must etch all deposited layers until the surface of the wafer is reached. Unlike HBTs, HEMTs are lateral, surface sensitive devices. This etch-back would result in direct bombarding of the device active channel and thus the deterioration of HEMTs' electrical characteristics.
FIG. 1A illustrates a tantalum nitride (TaN)/silicon nitride (SiN) resistor stack of the related art. Substrate 10 is shown having a layer 12 attached to substrate 10. Layer 12 is typically SiN. On top of layer 12, layer 14 is coupled. Layer 14 is typically TaN. To couple layer 14 to substrate 10, metallization layer 16 is used.
Since layer 12 is undercut with respect to layer 14 by the RIE etching process, metallization layer 16 must bridge the gap between layers 12 and 14. This gap does not provide proper support for metallization layer 16, and, as such, provides a stress point for metallization layer 16. Further, the height that metallization layer must span from the top of substrate 10 to the top of layer 14 is great (the “height” of the step is large), since layer 12 is sandwiched inbetween layer 14 and substrate 10. These factors lower the yield of devices and provide failure points for devices that survive initial fabrication and burn-in. Further, step coverage for metallization layer 16 is typically poor for devices using a structure as shown in FIG. 1A.
FIG. 1B illustrates a calibrated simulation of the device described in FIG. 1A. The stress point 18 for metallization layer 16 shows a discontinuous metallization layer 16. This occurs because of the void 20 created by the undercutting of layer 12 during the etching process.
A related process is described in “Thin-film tantalum-nitride resistor technology for phosphide-based optoelectronics,” M. L. Lovejoy, et al., Thin Solid Films 290-291 (1996), pages 513-517, which is incorporated by reference herein. The process described refers to TaN resistors and formation of TaN resistors without a SiN underlayer.
Another approach to fabricating the thin-film devices is through a liftoff process, as is conventionally done for metallization in ICs. However, thin films, such as TaN, are typically sputter deposited onto the wafer surface as contrasted with conventional metal evaporation, which is done from a “point source.” Conventional metal evaporation is a line of sight technique, and liftoff is essentially based on shadowing of the evaporated metal by a retrograde photoresist profile and the breakage of the metal at the edge of the photoresist.
However, since sputter deposition provides very good step coverage, the use of liftoff for sputtered thin films places additional requirements on the photoresist profiles used for liftoff of thin films. Experimental results from liftoff TaN thin film resistors creates edge buildup on the final resistor shape, which is undesired for later processing steps. The liftoff method is therefore expected to be a difficult and expensive task from the point of view of demand for exact photoresist profile optimization and possible lack of repeatability. It can be seen from the foregoing that there is a need in the art for providing thin film devices, such as resistors, that are compatible with HBT and HEMT devices. It can also be seen that there is a need in the art for a method for making thin film devices that do not degrade the HBT and HEMT devices.